The present invention relates to a semiconductor memory device, and more particularly, to a divided-bit line type dynamic random access memory having plural pairs of main bit lines, each of which is connected with plural pairs of sub-bit lines through the respective transfer gates.
Development of semiconductor memories continues in order to satisfy the ever-demanding high integration. To realize large-scale integrated dynamic random access memories (referred to as "dRAMs" hereinafter), the divided-bit line technique appears to be very promising. According to this technique, each of parallel bit line pairs formed on a substrate is connected to plural pairs of sub-bit lines via the respective transfer gates. When one memory cell is selected, the transfer gate of the sub-bit line pair to which the selected cell belongs, is opened and the read cell data voltage is supplied to a corresponding main bit line pair. A sense amplifier provided on the main bit line pair amplifies the read cell data voltage and then outputs it onto output lines. An example of the dRAM employing this technique is disclosed in "A 4Mb DRAM With Cross-point Trench Transistor Cell," Pallab K. Chatterjee et al., Digest of Technical Papers of 1986 IEEE International Solid-State Circuits Conference, pages 268 to 269.
However, dRAMs of this type have a difficulty in improving the data accessing speed and reducing the power consumption. It takes a sufficiently long period of time corresponding to the time required for the logical amplitude difference on the main bit line pair to become sufficiently large, from the point of time when one word line is designated for data readout from a desired cell to the point of time when the sense amplifier of the main bit line pair is made active. Since the sense amplifiers are of MOS dynamic type, the operation speed of the dRAM is reduced. According to the divided-bit line type dRAM, when the cell data is readout, sense amplifierse of the main bit line pairs, positioned along the selected word line, must be made active for the necessity of data restoring. As a result, the current flowing through the main bit lines is increased, which causes the dRAM to suffer from excessive power consumption.